1. Field of the Invention
The present invention relates generally to the field of computer aided design for digital circuits, and particularly to protecting design information contained in electronic design automation (EDA) models.
2. Description of the Related Art
Modern advances in silicon technology such as multi-layer deep sub-micron complimentary metal-oxide semiconductor (CMOS) technology are responsible for allowing larger and more complex designs to be formed on a single chip, and hence enabling entire “system-on-a-chip” (SOC) designs to be placed on the same silicon substrate. These complex designs may incorporate, for example, one or more processor components, a digital signal processing (DSP) component, memory, several communications interfaces, and a graphics support component.
The advent of SOC design has the electronic systems industry shifting toward a new design paradigm based on the use of preexisting circuit blocks or “cores.” Under this paradigm, systems are assembled by integrating one or more preexisting circuit blocks on the same silicon substrate. It is more efficient and practical for IC designers to incorporate components already developed rather than redesigning all the necessary hardware with each new IC design. It has naturally followed from this shift for different chip design vendors to supply preexisting circuit blocks to a system-level integrator or manufacturer developing a system-on-a-chip (SOC), and often these cores involve intellectual property (IP) owned by such vendors or groups other than the IC integrator.
As market demands continue to push electronic system manufacturers to develop systems more rapidly and efficiently, it is useful for the electronic system integrators or manufacturers to receive design models of a core to permit simulation and design integration of the SOC. An IC design simulation model allows an IC designer to know whether one component will work with another component to achieve the designer's needs. As the complexity of designs and methodologies increase, more and more detail and visibility into the core design is required to permit usability and integration. Unfortunately, the more accurate and detailed the model transferred to an SOC integrator, the greater the risk of misuse such as theft and unauthorized manipulation of those designs.
Core designs and models are relatively easy to copy, forge and re-design because they physically exist as data or code on storage devices. Moreover, the increased efficiency brought about by the existence of cores also provides an incentive for unauthorized use, re-use, transfer or sale of these items. As a consequence, while the complexity of designs and methodologies require transferring a significant amount of information to permit usability of the core by a SOC designer, it is becoming more important that efforts be taken to protect the IP transferred to customers, vendors and third parties participating in the SOC design.
Because the simulation model provides such valuable insight into the operation and capability of the design, those who own the IP in the design typically do not disclose the simulation model without carefully drafted legal agreements between the collaborating parties. Negotiating such agreements takes time and costs money for all parties. If a SOC designer wants to test out a design or idea, then procuring such agreements is a significant detriment to rapid, efficient and cost-effective design development. Moreover, by themselves, such legal means are of limited use because detection of illegal copying, forging, transfer or reuse of proprietary cores is difficult. It can be extremely challenging to determine whether a core was illegally acquired by a particular user or what sensitive information within a circuit design has been procured from its electronic form. Providers of cores are therefore in need of an effective method of protecting their designs so that they are not deprived of the benefits of the resources spent on design, development and procurement of cores.
In the following detailed description of exemplary embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific exemplary embodiments in which the invention may be practiced.